Technical Field
The present technique relates to the field of data processing.
Technical Background
A processing pipeline may support vector instructions for triggering execution of two or more lanes of processing. In response to the vector instruction, at least one micro-operation corresponding to the predicated vector instruction is issued to an execute stage, to control the execute stage to execute each of the required lanes of processing. Some implementations may issue separate micro-operations for each lane, while others could issue a combined micro-operation which triggers multiple lanes of processing. By triggering multiple lanes of processing in response to one instruction, this can improve performance and reduce code size. Some vector instructions may be predicated, so that masking of an effect of a given lane of processing is controlled based on a predicate register storing a predicate value. Predication can be used for controlling conditional execution of operations in each lane, or for controlling loop unrolling, for example.